Difference between revisions of "N200/N210"
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== Key Features== | == Key Features== | ||
===N200=== | ===N200=== | ||
| − | + | * Xilinx® Spartan® 3A-DSP 1800 FPGA | |
| − | + | * 14 bit 100 MS/s dual ADC | |
| − | + | * 16 bit 400 MS/s dual DAC | |
| − | + | * Frequency range: DC - 6 GHz with suitable daughterboard | |
| − | + | * Up to 50 MS/s in both directions | |
| − | + | * Full duplex, SISO (1 Tx & 1 Rx) | |
| − | + | * Fully-Coherent MIMO Capability | |
| − | + | * Optional GPSDO | |
| − | + | * Gigabit Ethernet connectivity | |
| − | + | ||
| − | + | ||
| − | + | ||
===N210=== | ===N210=== | ||
| − | + | * Xilinx® Spartan® 3A-DSP 3400 FPGA | |
| − | + | * 14 bit 100 MS/s dual ADC | |
| − | + | * 16 bit 400 MS/s dual DAC | |
| − | + | * Frequency range: DC - 6 GHz with suitable daughterboard | |
| − | + | * Up to 50 MS/s in both directions | |
| − | + | * Full duplex, SISO (1 Tx & 1 Rx) | |
| − | + | * Fully-Coherent MIMO Capability | |
| − | + | * Optional GPSDO | |
| − | + | * Gigabit Ethernet connectivity | |
| − | + | ||
| − | + | ||
| − | + | ||
==Compatible Daughterboards== | ==Compatible Daughterboards== | ||
| Line 50: | Line 44: | ||
* IIP3 (@ typ NF) 0 dBm | * IIP3 (@ typ NF) 0 dBm | ||
* Typical Noise Figure 5 dB | * Typical Noise Figure 5 dB | ||
| − | |||
| − | |||
| − | |||
==Physical Specifications== | ==Physical Specifications== | ||
| Line 67: | Line 58: | ||
[http://files.ettus.com/schematics/n200/n2xx.pdf N200/N210 Schematics] | [http://files.ettus.com/schematics/n200/n2xx.pdf N200/N210 Schematics] | ||
| − | == | + | ==Datasheets== |
| − | [http://www.analog.com/media/en/technical-documentation/data-sheets/AD9777.pdf AD9777] | + | * Dual Channel, 16-Bit DAC - [http://www.analog.com/media/en/technical-documentation/data-sheets/AD9777.pdf AD9777] |
| − | [http://www.ti.com/lit/ds/symlink/ads62p45.pdf ADS62P4X] | + | * Dual Channel, 14-Bit ADC - [http://www.ti.com/lit/ds/symlink/ads62p45.pdf ADS62P4X] |
| − | [http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf XC3SD3400AFG676] - Double check | + | * FPGA - [http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf XC3SD3400AFG676] - Double check |
| − | AD56x3 | + | * AD56x3 |
| − | [http://www.analog.com/media/en/technical-documentation/data-sheets/AD9510.pdf AD9510] | + | * Clock Distribution IC - [http://www.analog.com/media/en/technical-documentation/data-sheets/AD9510.pdf AD9510] |
| − | [http://download.siliconexpert.com/pdfs/2008/04/26/isys/lsi/ds06-161gphy_et1011c_09-28-2007.pdf ET1011C2] | + | * Gigabit Ethernet Transceiver - [http://download.siliconexpert.com/pdfs/2008/04/26/isys/lsi/ds06-161gphy_et1011c_09-28-2007.pdf ET1011C2] |
| − | [http://www.cypress.com/file/43236/download CY7C1354C] | + | * Pipelined SRAM - [http://www.cypress.com/file/43236/download CY7C1354C] |
| − | [http://www.ti.com/lit/ds/symlink/max232.pdf MAX232] | + | * Drivers/Receiver [http://www.ti.com/lit/ds/symlink/max232.pdf MAX232] |
| − | + | ||
| − | + | ||
| − | + | ||
==Mechanical Info== | ==Mechanical Info== | ||
| Line 108: | Line 96: | ||
[https://github.com/EttusResearch/uhd UHD Source Code on Github] | [https://github.com/EttusResearch/uhd UHD Source Code on Github] | ||
| + | |||
| + | |||
| + | ==Application Notes== | ||
| + | |||
| + | |||
| + | ==FAQ== | ||
[[Category:Product Resource Pages]] | [[Category:Product Resource Pages]] | ||
Latest revision as of 19:30, 18 April 2016
Contents
Device Overview
The USRP Network Series offers high-bandwidth, high-dynamic range processing capability. The Gigabit Ethernet interface of the USRP Network Series allows high-speed streaming capability up to 50 MS/s in both directions (8-bit samples). These features, combined with plug-and-play MIMO capability make the USRP Network an ideal candidate for software defined radio systems with demanding performance requirements.
Key Features
N200
- Xilinx® Spartan® 3A-DSP 1800 FPGA
- 14 bit 100 MS/s dual ADC
- 16 bit 400 MS/s dual DAC
- Frequency range: DC - 6 GHz with suitable daughterboard
- Up to 50 MS/s in both directions
- Full duplex, SISO (1 Tx & 1 Rx)
- Fully-Coherent MIMO Capability
- Optional GPSDO
- Gigabit Ethernet connectivity
N210
- Xilinx® Spartan® 3A-DSP 3400 FPGA
- 14 bit 100 MS/s dual ADC
- 16 bit 400 MS/s dual DAC
- Frequency range: DC - 6 GHz with suitable daughterboard
- Up to 50 MS/s in both directions
- Full duplex, SISO (1 Tx & 1 Rx)
- Fully-Coherent MIMO Capability
- Optional GPSDO
- Gigabit Ethernet connectivity
Compatible Daughterboards
- SBX-40
- UBX-40
- WBX-40
- CBX-40
- LFRX / LFTX
- BasicRX / BasicTX
- TVRX2
- DBSRX2
RF Specifications
RF Performance (with WBX)
- SSB/LO Suppression -35/50 dBc
- Phase Noise 1.8 GHz 10kHz -80 dBc/Hz
- Phase Noise 1.8 GHz 100kHz -100 dBc/Hz
- Phase Noise 1.8 GHz 1MHz -137 dBc/Hz
- Power Output 15 dBm
- IIP3 (@ typ NF) 0 dBm
- Typical Noise Figure 5 dB
Physical Specifications
Dimensions
22 x 16 x 5 cm
Environmental Specifications
Operating Temperature Range
- N200/N210 0-40 °C
Schematics
N200/N210
Datasheets
- Dual Channel, 16-Bit DAC - AD9777
- Dual Channel, 14-Bit ADC - ADS62P4X
- FPGA - XC3SD3400AFG676 - Double check
- AD56x3
- Clock Distribution IC - AD9510
- Gigabit Ethernet Transceiver - ET1011C2
- Pipelined SRAM - CY7C1354C
- Drivers/Receiver MAX232
Mechanical Info
Weight
1.2 kg
Drawings
FPGA
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Interfaces and Connectivity
N200/N210
- Gigabit Ethernet
Downloads (FPGA images, E310 images, etc.)
